通过Ada，我可以使用.ads和.adb文件将我的模块化单元分割成规格和主体。
是否有可能分离VHDL实体和体系结构？ 如果是这样，是否有这样的命名约定或推荐的风格？ 实体可以放在自定义库/包中吗？
With Ada I can split my modular units into specification and body with .ads and .adb files.
Is it possible to separate VHDL entity and architecture? If so, is there a naming convention or recommended style for doing this? And can the entities be placed in a custom library/package?
最满意答案
图书馆
一切都被编译成一个库。 默认情况下，这称为“工作”，但您可以覆盖它。 我很少使用它 - 如果存在命名空间冲突，它偶尔会对外部IP有用。 正如Chiggs评论的那样，使用库来创建命名空间是一种很好的做法。 大多数合成器现在可以处理多个库 ，但情况并非总是如此。 所有的模拟器都可以（据我所知）。 设置它们还有一些麻烦（你必须告诉编译器它们都在哪里）。
也许是一个例子 - 比如你有一个i2c控制器和一个spi控制器。 您可以调用两个块controller并将它们编译到自己的库中，称为i2c和spi ，然后像这样实例化它们：
i2c_instance:entity i2c.controller...etc spi_instance:entity spi.controller...etc或者你可以称它们为i2c_controller和spi_controller并执行：
i2c_instance:entity work.i2c_controller...etc spi_instance:entity work.spi_controller...etc和库不像硬盘文件夹“一样”。 它们由VHDL编译器管理，因此您可以使用该工具使用的任何语法创建并映射它们。
例如在Modelsim中， vlib在文件系统的特定位置创建一个库（所以它在这一点上看起来像一个文件夹）， vmap告诉编译器如何映射一个use some_lib; 子句到文件系统的特定位。
实体，架构，包
您可以将实体和体系结构（或每个实体甚至多个体系结构）分成多个文件，或将它们保存在一个文件中。 将architecture保存在单独的文件中意味着在重新编译它时，不要重新编译entity ，这意味着您不必重新编译实例化它的所有内容。
类似于packages和package body - 单独文件中的主体意味着您可以重新编译该部分而无需重新编译其他所有内容。 请注意， package不是用于放入实体的。
（另外 - Modelsim拥有一个“ -just开关，它允许您将所有内容保存在一个文件中，并仅对文件的选定位进行编译，例如，只包含architecture和/或body部分）
概要
将可重用的内核编译到其自己的库中以保护其名称空间 将其他所有内容编译到work库中 将有用的常量，函数，过程，类型定义放入一个或多个包中 将实体和体系结构放到一个或多个文件中比起其他任何事情都更符合品味和开发风格 将软件包和软件包体放入一个或多个文件是一个比其他任何事情都更具品味和开发风格的问题Libraries
Everything gets compiled into a library. By default this is called "work", but you can override this. I rarely have to use that though - it's occasionally useful with external IP if there are namespace clashes. As Chiggs commented, using libraries to create namespaces is a good practice. Most synthesizers can deal with multiple libraries now, although it wasn't always the case. All the simulators can (as far as I know). There's also a bit more hassle involved in setting them up (you have to tell the compiler where they all are).
maybe an example - say you have an i2c controller and an spi controller. You could call both blocks controller and compile them into their own libraries called i2c and spi and then instantiate them like this:
i2c_instance:entity i2c.controller...etc spi_instance:entity spi.controller...etcor you could call them i2c_controller and spi_controller and do:
i2c_instance:entity work.i2c_controller...etc spi_instance:entity work.spi_controller...etcAnd libraries are not "just the same" as hard disk folders. They are managed by the VHDL compiler, so you create and map them using whatever syntax the tool uses.
For example with Modelsim, vlib creates a library at a particular place in the filesystem (so it does look like a folder at this point) and vmap tells the compiler how to map a use some_lib; clause to a particular bit of the filesystem.
Entities, architectures, packages
You can separate your entity and architecture (or even more than one architecture per entity) into multiple files, or keep them in one file. Keeping the architecture in a separate file means that when you recompile it, you don't recompile the entity, which means you don't have to recompile everything that instantiates it.
Similarly with packages and package bodys - bodies in a separate file means you can just recompile that part without recompiling everything else. Note that packages are not for putting entities in.
(Aside - Modelsim has a -just switch that allows you to keep everything in one file and just compile selected bits of the files, for example, just the architecture and/or body part(s))
Summary
Compile re-useable cores into their own library to protect their namespace Compile everything else into the work library Put useful constants, functions, procedures, type definitions into one or more packages Putting entities and architectures into one or more files is a matter of taste and development style more than anything else Putting packages and package bodies into one or more files is a matter of taste and development style more than anything else更多推荐
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